1. Field of the Invention
This invention relates generally to clocked operations in electronic devices, and more particularly to managing timing of performance of these operations.
2. Related Art
Because it is expensive to set up fabrication of integrated circuit (“IC”) chips, and because chips having huge numbers of transistors are complicated and subject to design glitches, it is common when designing a chip to extensively test an emulated version of the chip before fabrication. Furthermore, it is quite common for chips to interface with one another. In emulation and testing, the emulated version of a chip under development may be interfaced with and tested together with another, actual IC chip.
In order for IC chips to properly work together, the chips often send or receive an external clock for synchronizing and for generating an internal clock. The internal clock typically uses a phase locked loop (“PLL”) to run at a higher speed than the external clock, such as twice (“2×”) the external clock frequency, for example. For emulation and testing, the maximum clock speed at which the emulated chip is capable of operating is very slow in comparison with the operating frequency of the actual chip. Consequently, the external clock, which serves as a reference to both the emulated and actual chips, must run so slowly that the internal clocks for the chips cannot be generated from the external clock, due to limitations in conventional clock generation circuitry.
Emulation system constraints, therefore, commonly demand that external and internal clocks operate at the same speed, referred to as a “1:1 mode” or “PLL bypass mode.” This, however, leads to complications. For example, frequently a chip is supposed to generate a response to some event within a certain number of external clock cycles. However, as described above, when not in 1:1 mode a certain number of external clock cycles ordinarily corresponds to a larger number of internal clock cycles. When the chip is operating in 1:1 mode, the required response time may be inadequate as measured in terms of the now slower, internal clock. Therefore, a need exists for improvements in the capability of chips to operate responsive to a slowed down clock.